The present invention relates to a voltage output digital-to-analog converter circuit.
A voltage output digital-to-analog converter circuit has a plurality of switching elements which switch their connection states according to respective bits of an input digital signal and a resistor network formed by connecting, in a so-called “ladder-type” manner, resistors of two types which are selected such that the ratio between their resistance values is 1:2.
The voltage output digital-to-analog converter circuit switches the connection state of each switching element to the reference voltage terminal or the ground terminal according to a digital signal input as a corresponding bit and divides the reference voltage using the resistor network, thereby generating an output voltage corresponding to the input digital signal, i.e., an output analog signal (see, e.g., Toshikazu Yoneyama, “Introduction to A/D Converters”, Ohmsha, Ltd., pp. 139-140).
Each switching element is formed by, e.g., connecting a source of PMOS transistor and a source of NMOS transistor to the reference voltage terminal and the ground terminal respectively. Each of the PMOS transistor and NMOS transistor generates an on-resistance having a certain resistance value using a MOS transistor when it is on.
For this reason, if the PMOS transistor connected to the reference voltage terminal is turned on, the NMOS transistor connected to the ground terminal is turned off, and the reference voltage is selected, a problem arises. More specifically, since the PMOS transistor has the on-resistance, the on-resistance is series-connected to the resistor connected to the switching element, and an error occurs in the output voltage, i.e., analog signal.